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ispLSI 1032/883
(R)
In-System Programmable High Density PLD Features
* HIGH-DENSITY PROGRAMMABLE LOGIC -- High Speed Global Interconnect -- 6000 PLD Gates -- 64 I/O Pins, Eight Dedicated Inputs -- 192 Registers -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Fast Random Logic -- Security Cell Prevents Unauthorized Copying * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 60 MHz Maximum Operating Frequency -- tpd = 20 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology -- 100% Tested * IN-SYSTEM PROGRAMMABLE -- In-System ProgrammableTM (ISPTM) 5-Volt Only -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Four Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0 A0 C7
Output Routing Pool
A2 A3 A4
Logic Array
DQ
C5
DQ
GLB
C4 C3
DQ
A5 A6 A7
C2 C1
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
C0
CLK
Output Routing Pool
Description
The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032/883 features 5-Volt in-system programming and in-system diagnostic capabilities. It is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 1032/883 device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see figure 1). There are a total of 32 GLBs in the ispLSI 1032/883 device. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
1032MIL_01
1
Output Routing Pool
A1
DQ
C6
Specifications ispLSI 1032/883
Functional Block Diagram
Figure 1. ispLSI 1032/883 Functional Block Diagram
I/O I/O I/O I/O 63 62 61 60 RESET I/O I/O I/O I/O 59 58 57 56 I/O I/O I/O I/O 55 54 53 52 I/O I/O I/O I/O 51 50 49 48 IN IN 76
Input Bus Generic Logic Blocks (GLBs) D7 D6 Output Routing Pool (ORP) D5 D4 D3 D2 D1 D0
IN 5 IN 4 I/O 47 I/O 46 I/O 45 I/O 44
C7
I/O 0 I/O 1 I/O 2 I/O 3
A0 A1
Output Routing Pool (ORP)
C6
Output Routing Pool (ORP)
C5 C4 C3 C2 C1 C0
I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32
Input Bus
A3 A4 A5 A6 A7
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1
Global Routing Pool (GRP)
B0
B1
B2
B3
B4
B5
B6
B7
Clock Distribution Network
Megablock
Output Routing Pool (ORP) Input Bus
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
ispEN SDO/IN 2 SCLK/IN 3 I/O I/O I/O I/O 16 17 18 19 I/O I/O I/O I/O 20 21 22 23 I/O I/O I/O I/O 24 25 26 27 I/O I/O I/O I/O 28 29 30 31 YYYY 0123
0139(1)-32-isp
The device also has 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The I/O cells within the Megablock also share a common Output Enable (OE) signal. The ispLSI 1032/883 device contains four of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1032/883 device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI 1032/883 device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
2
lnput Bus
I/O 4 I/O 5 I/O 6 I/O 7
A2
Specifications ispLSI 1032/883
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Military/883 TC = -55C to +125C MIN. 4.5 0 2.0 MAX. 5.5 0.8 Vcc + 1 V V
0005A mil.eps
UNITS
VCC VIL VIH
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O and Clock Capacitance MAXIMUM1 10 10 UNITS pf pf TEST CONDITIONS VCC=5.0V, VIN=2.0V VCC=5.0V, VI/O, VY=2.0V
Table 2- 0006mil
C1 C2
1. Characterized but not 100% tested.
Data Retention Specifications
PARAMETER Data Retention Erase/Reprogram Cycles MINIMUM 20 10000 MAXIMUM -- -- UNITS Years Cycles
Table 2- 0008B
3
Specifications ispLSI 1032/883
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See figure 2
Figure 2. Test Load
+ 5V R1 Device Output R2 CL* Test Point
3-state levels are measured 0.5V from steady-state active level.
Table 2- 0003
Output Load Conditions (see figure 2)
*CL includes Test Fixture and Probe Capacitance.
Test Condition A B Active High Active Low C Active High to Z at VOH - 0.5V Active Low to Z at VOL + 0.5V R1 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
470
470
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current isp Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL =8 mA IOH =-4 mA 0V VIN VIL (MAX.) 3.5V VIN VCC 0V VIN VIL (MAX.) 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V fTOGGLE = 1 MHz 1. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using six 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25oC. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC. 0007A-32 mil CONDITION MIN. - 2.4 - - - - - - TYP. 3 - - - - - - - 135 MAX. 0.4 - -10 10 -150 -150 -200 220 UNITS V V A A A A mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1
ICC2,4
4
Specifications ispLSI 1032/883
External Timing Parameters
Over Recommended Operating Conditions
52 PARAMETER TEST #
COND.
DESCRIPTION1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback (tsu2 1 tco1) + Clock Frequency, Max Toggle4 GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock - - 60 38 83 9 - 0 13 - 0 - 13 - - 6 6
-60
MIN. MAX. 20 25 - - - - 13 - - 16 - 22.5 - 24 24 - - - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5
1. 2. 3. 4. 5.
A A A - - - A - - - - A - B C - - - -
1 2 3 4 5 6 7 8 9
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Ext. Sync. Clock Pulse Duration, High 17 Ext. Sync. Clock Pulse Duration, Low 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
2.5 8.5
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section.
Table 2-0030-32/60C
5
Specifications ispLSI 1032/883
Internal Timing Parameters1
2
PARAMETER
#
DESCRIPTION
-60
MIN. MAX.
UNITS
Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16 tgrp32 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp
20 21 22 23 24 25 26
I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay
- - 7.3 1.3 - - -
2.7 4.0 - - 4.0 3.3 5.3
ns ns ns ns ns ns ns
27 28 29 30 31 32
GRP Delay, 1 GLB Load GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 12 GLB Loads GRP Delay, 16 GLB Loads GRP Delay, 32 GLB Loads
- - - - - -
2.0 2.7 4.0 5.0 6.0 10.6
ns ns ns ns ns ns
33 34 35 36 37 38 39 40 41 42 43 44
4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay 20 Product Term/XOR Path Delay XOR Adjacent Path Delay3 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay
- - - - - 1.3 6.0 - - - - 4.6
8.6 9.3 10.6 12.7 1.3 - - 2.7 3.3 13.3 12.0 9.9
ns ns ns ns ns ns ns ns ns ns ns ns
45 46
ORP Delay ORP Bypass Delay
- -
3.3 0.7
ns ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice Hard Macros.
6
Specifications ispLSI 1032/883
Internal Timing Parameters1
2
PARAMETER
#
DESCRIPTION
-60
MIN. MAX.
UNITS
Outputs tob toen todis Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp
47 48 49
Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled
- - -
4.0 6.7 6.7
ns ns ns
50 51 52 53 54
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line
6.0 4.6 1.3 4.6 1.3
6.0 7.3 6.6 7.3 6.6
ns ns ns ns ns
Global Reset tgr 55
Global Reset to GLB and I/O Registers
-
12.0
ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
7
Specifications ispLSI 1032/883
ispLSI 1032/883 Timing Model
I/O Cell GRP Feedback Ded. In GLB ORP I/O Cell
#26 I/O Reg Bypass #20 Input D Register Q RST #21 - 25 GRP 4 #28 GRP Loading Delay #27, 29, 30, 31, 32 4 PT Bypass #33 20 PT XOR Delays #34, 35, 36 #55 D RST #38, 39, 40, 41 GLB Reg Bypass #37 GLB Reg Delay Q ORP Bypass #46 ORP Delay #45 #47 I/O Pin (Output) #48, 49
I/O Pin (Input)
#55 Reset
Clock Distribution Y1,2,3 #51, 52, 53, 54 #50
Control RE PTs OE #42, 43, CK 44
Y0
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) 7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (2.7 + 2.7 + 4.6)
th
= Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) 5.3 ns = (2.7 + 2.7 + 9.9) + (6.0) - (2.7 + 2.7 + 10.6)
tco
= Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 25.3 ns = (2.7+ 2.7 +9.9) + (2.7) + (3.3 + 4.0)
Derivations of tsu, th and tco from the Clock GLB1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) = (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) 7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (6.0 + 2.7 + 1.3)
th
= Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) 5.3 ns = (6.0 + 2.7 + 6.6) + (6.0) - (2.7 + 2.7 + 10.6)
tco
= Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) 25.3 ns = (6.0 + 2.7 + 6.6) + (2.7) + (3.3 + 4.0) 1. Calculations are based upon timing specifications for the ispLSI 1032-60.
8
Specifications ispLSI 1032/883
Maximum GRP Delay vs GLB Loads
6 5
GRP Delay (ns)
ispLSI 1032-60
4 3 2 1 0 4 8 GLB Loads 12 16
0126A-80-32-mil
Power Consumption
Power consumption in the ispLSI 1032/883 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax
250
used. Figure 3 shows the relationship between power and operating speed.
ICC (mA)
200 150 100 50 0 10 20 30
ispLSI 1032
40
50
60
70
80
fmax (MHz)
Notes: Configuration of eight 16-bit Counters Typical Current at 5V, 25C
ICC can be estimated for the ispLSI 1032 using the following equation: ICC = 52 + (# of PTs * 0.30) + (# of nets * Max. freq * 0.009) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A-32-80-isp
9
Specifications ispLSI 1032/883
Pin Description
Name
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 IN 4 - IN 7 ispEN
CPGA Pin Numbers
F1, K1, K3, L4, L7, K8, L11, J11, E9, B11, B9, A8, A5, B4, A1, C1, H1, J2, L2, J5, K7, L9, K10, H10, D11, C10, A10, B6, B5, A3, B2, D2, H2, L1, L3, K5, L6, L10, J10, H11, D10, A11, A9, B7, C5, A2, C2, D1, A6, J1, K2, K4, L5, L8, K9, K11, F10, C11, B10, B8, A7, A4, B3, B1, E3 E2
Description
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
E10, C7, G3
Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. No Connect
SDI/IN 01
G2
MODE/IN 11
K6
SDO/IN 21
J7
SCLK/IN 31
G10
RESET Y0 Y1
G1 E1 E11
Y2
G9
Y3
G11
NC2
G3
GND
VCC
C6, F2,
F3, F11
F9,
J6
Ground (GND) VCC
Table 2-0002-32/883
1. Pins have dual function capability. 2. NC pins are not to be connected to any active signals, Vcc or GND.
10
Specifications ispLSI 1032/883
Pin Configuration
ispLSI 1032/883/883 84-Pin CPGA Pinout Diagram
11
I/O38
10
I/O41
9
I/O42
8
I/O44
7
I/O47
6
IN6
5
I/O48
4
I/O51
3
I/O53
2
I/O54
1
I/O56
PIN A1
A
I/O36
I/O39
I/O40
I/O43
I/O46
I/O45
I/O49
I/O52
I/O55
I/O57
I/O59
B
I/O35
I/O37
IN5
GND
I/O50
INDEX
I/O58
I/O60
C
I/O33
I/O34
I/O61
I/O62
D
Y1
IN4
I/O32
I/O63
IN7
Y0
E
Vcc
I/O31
GND
ispLSI 1032/883
Bottom View
GND
Vcc
I/O0
F
Y3
*SCLK/ IN3
Y2
ispEN
*SDI/ IN0
RESET
G
I/O30
I/O29
I/O2
I/O1
H
I/O28
I/O26
*SDO/ IN2
GND
I/O13
I/O5
I/O3
J
I/O27
I/O25
I/O23
I/O20
I/O17
*MODE/ IN1
I/O14
I/O11
I/O8
I/O7
I/O4
K
I/O24
I/O22
I/O21
I/O19
I/O16
I/O18
I/O15
I/O12
I/O10
I/O9
I/O6
L
*Pins have dual function capability.
0488A-32-isp/883
11
Specifications ispLSI 1032/883
Part Number Description
ispLSI 1032 - XX
Device Family
X
X
X
Grade /883 = 883 Military Process
Device Number Package G = CPGA
Speed 60 = 60 MHz fmax
Power L = Low
0212-80B-isp1032
Ordering Information
MILITARY/883 Family ispLSI
fmax (MHz) tpd (ns)
60 20
Ordering Number ispLSI 1032-60LG/883
SMD Number 5962-9308501MXC
Package 84-Pin CPGA
Table 2- 0041A-32-ispmil
Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended.
12

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